Plug via formation by patterned plating and polishing

ABSTRACT

Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. A via opening extends through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer. A mask on the top surface of the passivation layer includes a mask opening that is aligned with the via opening. A conductive layer is selectively formed in the via opening and the mask opening. The conductive layer projects above the top surface of the passivation layer. The method further includes planarizing the passivation layer and the conductive layer to define a plug in the via opening that is coupled with the metal line.

BACKGROUND

The invention relates generally to semiconductor structures andfabrication of semiconductor chips and, in particular, to solder bumpconnections and methods for fabricating solder bump connections duringback-end-of-line processing of semiconductor chips.

A chip or die includes integrated circuits formed by front-end-of-lineprocessing, a local interconnect layer formed by middle-end-of-lineprocessing, and stacked metallization levels of an interconnectstructure formed by back-end-of line processing. Chips may be packagedand mounted on a circuit board or other chip carrier using a controlledcollapse chip connection or flip chip process. The solder bumps providemechanical and electrical connections between features in the last ortop metallization level and the circuit board. The solder bumps can beformed using any number of methods, including electroplating,evaporation, printing, and direct placement. The solder bumps establishphysical attachment and electrical contact between an array of pads onthe chip and a complementary array of pads on a circuit board.

Solder bump connections and fabrication methods are needed that improveon conventional solder bump connections and fabrication methods.

SUMMARY

In an embodiment of the invention, a method is provided for fabricatinga solder bump connection. The method includes forming a passivationlayer on a dielectric layer, forming a via opening extending through thepassivation layer from a top surface of the passivation layer to a metalline in the dielectric layer, and forming a mask on the top surface ofthe passivation layer. A mask opening in the mask is aligned with thevia opening. The method further comprising selectively forming aconductive layer in the via opening and the mask opening. The conductivelayer projects above the top surface of the passivation layer. Themethod further includes planarizing the passivation layer and theconductive layer to define a plug in the via opening that is coupledwith the metal line.

In an embodiment of the invention, a solder bump connection includes avia opening extending through a passivation layer and a plug in the viaopening. The plug is comprised of a conductor, and the passivation layerincludes a top surface that is coplanar with the plug and that is freeof surface damage.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate various embodiments of theinvention and, together with a general description of the inventiongiven above and the detailed description of the embodiments given below,serve to explain the embodiments of the invention.

FIGS. 1-6 are cross-sectional views of a portion of a substrate atsuccessive stages of a processing method for fabricating a devicestructure in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

With reference to FIG. 1 and in accordance with an embodiment of theinvention, a topmost metallization level of a back-end-of-line (BEOL)interconnect structure, generally indicated by reference numeral 10,includes a plurality of dielectric layers 12, 14, as well as a metalline 16 and a plurality of metal features 18 embedded as metallizationin one or more of the dielectric layers 12, 14. In the representativeembodiment, the metal line 16 is adjacent to the metal features 18 andthe metal features 18 are near a scribe line for the substrate. Typicalconstructions for the BEOL interconnect structure consist of two or moreindividual metallization levels. The metallization levels of the BEOLinterconnect structure are formed by deposition, lithography, etching,and polishing techniques characteristic of damascene processesassociated with BEOL processing.

Each of the dielectric layers 12, 14 may be comprised of an organic orinorganic dielectric material that is an electrical insulator with anelectrical resistivity at room temperature of greater than 10¹⁰ (Ω-m) isdeposited. Candidate inorganic dielectric materials for dielectriclayers 12, 14 may include, but are not limited to, silicon dioxide,fluorine-doped silicon glass (FSG), and combinations of these dielectricmaterials. Alternatively, the dielectric layers 12, 14 may be comprisedof a low-k dielectric material characterized by a relative permittivityor dielectric constant smaller than the SiO₂ dielectric constant ofapproximately 3.9. Candidate low-k dielectric materials for dielectriclayers 12, 14 include, but are not limited to, porous and nonporousspun-on organic low-k dielectrics (e.g., thermoset polymer resins),porous and nonporous inorganic low-k dielectrics (e.g., organosilicateglasses, hydrogen-enriched silicon oxycarbide (SiCOH), and carbon-dopedoxides), and combinations of these and other organic and inorganicdielectrics. Dielectric layers 12, 14 may be deposited by any number oftechniques including, but not limited to, sputtering, spin-onapplication, or CVD.

The metal line 16 and the metal features 18 may be comprised of copper,aluminum, or an alloy of these materials, and may be formed by adamascene process in the dielectric layers 12, 14. The metal line 16 maybe slotted or “cheesed” to limit current crowding.

The BEOL interconnect structure is carried on a die or chip that hasbeen processed by front-end-of-line processes to fabricate one or moreintegrated circuits that contain device structures and middle-end-ofline processes to fabricate a local interconnect structure. The chip maybe formed using a wafer of semiconductor material suitable forintegrated circuit fabrication.

A layer stack including a capping layer 20 and dielectric layers 22, 24may be formed on a top surface 14 a of dielectric layer 14. The cappinglayer 20 may be comprised of a material such as Si_(w)C_(x)N_(y)H_(z),and the dielectric layers may be comprised of silicon nitride (Si₃N₄)and silicon dioxide (SiO₂).

The layer stack may be patterned to define a via opening 26 and acrackstop opening 28 in the dielectric layers 12, 14. To that end, amask layer may be applied on the top surface of dielectric layer 24 andlithographically patterned with photolithography process to defineopenings coinciding with the intended locations of openings 26, 28. Themask layer may comprise a light-sensitive material, such as aphotoresist, that is applied as a coating by a spin coating process,pre-baked, exposed to light projected through a photomask, baked afterexposure, and developed with a chemical developer to form an etch maskthat includes the openings. The pattern of openings in the mask layer istransferred by the etching process from the mask layer to the dielectriclayers 12, 14. The etching process may comprise a wet chemical etchingprocess or a dry etching process, such as reactive-ion etching (RIE).The etching process, which may be conducted in a single etching step ormultiple steps, relies on one or more etch chemistries to etch thematerials of dielectric layers 12, 14 while substantially not etchingthe dielectric material of the capping layer 20 acting as an etch stop.The mask layer is removed after the openings 26, 28 are formed (e.g., byashing or solvent stripping if the mask layer is comprised ofphotoresist), followed by a cleaning process.

A patterned passivation layer 30 is formed that includes a via opening32 and a crackstop opening 34. The passivation layer 30 may be comprisedof an organic material, such as a polymer, that is optionallyphotosensitive and that is an electrical insulator. The passivationlayer 30 may be comprised of photosensitive polyimide (PSPI) or anotherorganic material such as photosensitive polybenzoxazole (PBO). Thepassivation layer 30 may be prepared by dissolving the polymer in asolvent to form a precursor, spreading the precursor with a spin coatingprocess as a coating across dielectric layer 24, and then drying thecoating to remove solvents.

The via opening 32 extends through the entire layer thickness of thepassivation layer 30 at the location of via opening 26. The via opening32 may be considered to be an extension of via opening 26 and totherefore be continuous with via opening 26 so that a single compositevia opening extends from the top surface 30 a to the metal line 16. Thevia openings 26, 32 may have the same nominal lateral dimensions (e.g.,the same width). The location of the via openings 26, 32 defines anintended position for forming a solder bump connection, and spatiallycoincides with the location of opening 26 in the dielectric layers 12,14.

The crackstop opening 34 extends through the entire layer thickness ofthe passivation layer 30 at the location of the crackstop opening 28.The crackstop opening 34 may be considered to be an extension ofcrackstop opening 28 and to therefore be continuous with crackstopopening 28 so that a single composite crackstop opening extends from thetop surface 30 a to the uppermost feature of the metal features 18. Thecrackstop opening 34 may have larger dimensions (e.g., a larger width)than the crackstop opening 28. The location of the crackstop openings28, 34 defines an intended position for a crackstop that serves as abarrier for the propagation of cracks inward from an outer edge of thedie or a kerf region as might occur, for example, during dicing.

If the passivation layer 30 is comprised of a photosensitive material,the passivation layer 30 may be lithographically patterned by radiationexposure and exposure to a wet chemical developer to define the openings32, 34. The precursor coating is subsequently cured to imidize andcrosslink the polymer. If the passivation layer 30 is comprised of anon-photosensitive material, a photoresist may be spun onto thepassivation layer 30, exposed using radiation projected through aphotomask, and then developed to form windows at the intended locationsfor the openings 32, 34. Using the patterned photoresist as an etchmask, the openings 32, 34 may be formed in the passivation layer 30 witha wet chemical etch process.

The capping layer 20 is removed from within the openings 26, 28. Theremoval of the capping layer 20 can be performed, for example, using asputter etch with energetic noble gas ions (e.g., positively-chargedargon ions) or a RIE. The passivation layer 30 may be cleaned, forexample, using a chromic-phosphoric acid solution.

With reference to FIG. 2 in which like reference numerals refer to likefeatures in FIG. 1 and at a subsequent fabrication stage, a layer stackincluding an adhesion layer 36 and a seed layer 38 is formed that coversthe sidewalls of the aligned set of openings 26, 32 and the metal line16, that covers the sidewalls of the aligned set of openings 28, 34 andthe stepped profile at the base created by the larger size of opening34, and on the passivation layer 30. The adhesion layer 36 may directlycontact the seed layer 38 so that layers 36, 38 are in physical andelectrical contact. The adhesion layer 36 is in physical and electricalcontact with the metal line 16 and with the metal features 18, and mayalso act as a diffusion barrier in addition to promoting the adhesion ofthe seed layer 38 with the passivation layer 30 and/or the metal line16.

The adhesion layer 36 may be comprised of titanium (Ti), titaniumnitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a multilayercombination of these materials (e.g., a bilayer of TaN/Ta). In oneembodiment, seed layer 38 may be comprised of copper (Cu), such aselemental Cu or co-deposited chromium-copper (Cr-Cu). The adhesion layer36 and the seed layer 38 may each have a thickness in a range of 10 nmto 100 nm. The layers 36, 38 of the layer stack may be seriallydeposited using, for example, physical vapor deposition (PVD).

A patterned plating mask 40 is formed by applying a resist layer,exposing the resist layer to radiation through a photomask, anddeveloping the exposed resist layer to form an opening 42 at thelocation that spatially coincides with the aligned set of via openings26, 32 reaching to the metal line 16, but that has larger dimensionsthan via opening 32. A portion of the plating mask 40 fills the alignedset of crackstop openings 28, 34.

A conductive layer 44 is formed that fills and adopts the geometricalshape of the aligned set of openings 26, 32, 42. The conductive layer 44may be comprised of Cu, although other suitable low-resistivity metalsand metal alloys may be selected. The conductive layer 44 may bedeposited by a deposition process that does not generate an overburdenof conductor on the top surface 40 a of the plating mask 40, such as anelectrochemical plating process like electroplating. The selectivedeposition process contrasts with other non-selective depositionprocesses, such as PVD, that are capable of producing a thick conductoroverburden on the top surface 40 a. In an electrochemical platingprocess, the exposed seed layer 38 inside the aligned set of openings26, 32, 42 operates as a catalyst to nucleate the formation of theconductor constituting conductive layer 44. The layers 36, 38 may coverthe entire surface of the wafer, which provides a good conduction pathfor electroplating currents. The material in seed layer 38 may besubsumed during the deposition process, such that the seed layer 38 maybecome continuous with or blend into conductive layer 44.

The plating mask 40 covers the seed layer 38 in field regions outside ofthe vicinity of the opening 42 so that the seed layer 38 cannot initiateconductor growth in the field. The deposition of the conductive layer 44is also constrained by the dimensions of the openings 26, 32, 42 and thetop surface 40 a of the plating mask 40 is free of the conductor. A plug41 comprised of the conductor of conductive layer 44 resides inside thealigned set of openings 26, 32, 42 and may be considered to constitute acomponent of the under-bump metallurgy. The plug 41 in is directphysical and electrical contact with the top surface 38 a of the seedlayer 38 inside the aligned set of openings 26, 32, 42. Alternatively,if the seed layer 38 is considered to be subsumed into the material ofthe plug 41, the plug 41 and the adhesion layer 36 may be considered tobe in physical and electrical contact inside the aligned set of openings26, 32, 42.

The conductive layer 44 may be deposited with a thickness that isgreater than or equal to the thickness of the passivation layer 30. Atypical thickness for the conductive layer 44 may be greater than orequal to 4 microns, which is at least an order of magnitude thicker thanthe seed layer 38 and/or the adhesion layer 36. The excess conductorthickness is needed so that the plug 41 can be fully planarized (i.e.,lacks a topographical depression or divot after planarization). Fullplanarization of the plug 41 may minimize Chip-Package-Interaction(CPI)-induced risks, such as a risk of delamination, that mightotherwise cause reliability concerns during flip-chip assemblyprocesses. Because the opening 42 in plating mask 40 is larger in sizethan the opening 32 in passivation layer 30, sections 45 of theconductive layer 44 are joined with the edges of the plug 41 and projectabove the top surface 30 a of passivation layer 30. The sections 45 ofthe conductive layer 44 in the space between the mask opening 32 andmask opening 42 also partially overlap with the top surface 30 a of thepassivation layer 30.

With reference to FIG. 3 in which like reference numerals refer to likefeatures in FIG. 2 and at a subsequent fabrication stage, the platingmask 40 is stripped or otherwise removed from the top surface 30 a ofthe passivation layer 30. The field surrounding the aligned set ofopenings 26, 32, 42 is free of the conductor from the conductive layer44 other than the minor overlap of the sections 45. However, the plug 41and the sections 45 of conductive layer 44 adjoining plug 45 projectabove the top surface 30 a of the passivation layer 30 to generate adivoted topography.

With reference to FIG. 4 in which like reference numerals refer to likefeatures in FIG. 3 and at a subsequent fabrication stage, a polishingprocess is used to planarize the plug 41 relative to the top surface 30a of the passivation layer 30. At the conclusion of the polishingprocess, the top surface 41 a of the plug 41 is coplanar with the topsurface 30 a of the passivation layer 30. In one embodiment, achemical-mechanical polishing (CMP) process may be used to removesurface topography and provide the flattening. The CMP process combinesabrasion and chemical erosion to remove the peripheral sections 45 andto reduce the thickness of the plug 41. This polishing process or adifferent polishing process may be used to remove the adhesion layer 36and seed layer 38 from the top surface 30 a of the passivation layer 30.At the conclusion of the polishing, the top surface 30 a of thepassivation layer 30 is visible.

The polishing process is controlled to eliminate or limit contact of thepolish pad with the top surface 30 a of the passivation layer 30. Theeliminated or limited contact limits the amount of surface damage(features such as scratches and gouges) and other defects created in topsurface 30 a. The top surface 30 a may be considered to be free ofsurface damage or free of surface damage within a small tolerance for aminor amount of surface damage. The avoided or reduced damage to the topsurface 30 a may improve its visual appearance by reducing defectintroduction and improve the interfacial reliability with contactingpackaging materials, like underfill. The reduction in surface damage mayalso reduce the amount of metal (e.g., the materials comprising theconductive layer 40 and the adhesion layer 36) embedded in the surfacefeatures comprising the damage.

The extent of the potential damage is related to the polishing processtime beyond the nominal point of surface clearance (i.e., over-polishingbeyond the “endpoint”) to provide the planarization. A factorinfluencing this over-polish time beyond endpoint is the thickness ofthe conductive layer 44 deposited on the top surface 30 a of thepassivation layer 30. As mentioned previously, the layer thickness ischosen to ensure the plug 41 can be fully planarized. The over-polishtime required to adequately clear the surface of the conductoroverburden increases with increasing conductor thickness, whichincreases the contact between the polishing pad and the top surface 30a. The use of patterned plating involving the plating mask 40 and adeposition process that selectively forms the conductive layer 44without depositing conductor on the top surface 40 a of the plating mask40 in the field surrounding the via opening 42 reduces the overburdenrequirement of conductor to be removed. The extent of the conductoroverburden is limited to conductor in the space between the via openings32, 42. As a result, the polishing process may reach the endpointcomparatively quickly, and the amount of overpolish can be reduced dueto the almost complete absence of conductor overburden. The only sourcesof overburden in the field are the adhesion layer 36 and the seed layer38, each of which is thin in comparison with the conductive layer 44.The reduction in the over-polish time may also improve the thicknessuniformity of the passivation layer 30, and reduce notching at thejunction between the passivation layer 30 and the adhesion layer 36 atthe intersection of the via opening 32 with the top surface 30 a of thepassivation layer 30.

The top surface 30 a of passivation layer 30 and the top surface 41 a ofplug 41 may be cleaned. For example, the top surfaces 30 a, 41 a may besputter cleaned using energetic positive argon ions.

A layer stack including an adhesion layer 46 and a seed layer 48 isformed that covers top surface 30 a of passivation layer 30 and the topsurface 41 a of plug 41, and that covers the sidewalls of the alignedset of openings 28, 34 and the stepped profile at the base created bythe larger size of opening 34. The adhesion layer 46 may directlycontact the seed layer 48 so that layers 46, 48 are in physical andelectrical contact. The layers 46, 48 are components of Ball LimitingMetallurgy (BLM) or Under Bump Metallurgy (UBM). The adhesion layer 46may be comprised of one or more refractory metals that are thermallystable during BEOL processes and that strongly adhere with thesubsequently-formed pedestal. The adhesion layer 46 may be comprised of,for example, titanium tungsten (TiW), and the seed layer 48 may becomprised of Cu or Cr-Cu. Layers 46, 48 of the layer stack may beserially deposited using, for example, PVD.

With reference to FIG. 5 in which like reference numerals refer to likefeatures in FIG. 4 and at a subsequent fabrication stage, a patternedplating mask 50 is formed by applying a layer of a photo-sensitiveorganic material, exposing the photosensitive organic material in thelayer to radiation through a photomask, and developing the exposedphotosensitive organic material to form an opening 52 in the layer at alocation that spatially coincides with the plug 41. In one embodiment,the plating mask 50 may be a photoactive polymer resist, such as RISTON®photopolymer resist. The plating mask 50 fills the aligned set ofopenings 28, 34 and the opening 52 determines the shape, thickness, andlocation of a pedestal and solder bump. The dimensions of the opening 52in the plating mask 50 may match a specification for solder bumping and,in particular, may match the specification for C4 solder bumping. Inparticular, the size of the opening 52 is a factor in determiningdimensions (length and width) of the pedestal and solder bump and thethickness of the plating mask 50 is a factor in determining the heightof the pedestal and solder bump.

A pedestal comprised of barrier layers 54, 58 and a conductor layer 56disposed between the barrier layers 54, 58 is formed within the opening52 in the plating mask 50. The barrier layer 54 may be formed on a topsurface of the seed layer 48 overlying the plug 41. The conductor layer56, which is comprised of a different material, such as Cu, is formed ona top surface of the barrier layer 54. The barrier layer 58 may beformed on a top surface of the conductor layer 56. The barrier layers54, 58 and conductor layer 56 do not form on the plating mask 50. In arepresentative embodiment, the barrier layers 54, 58 may be comprised ofa metal, such as nickel (Ni) or a Ni alloy (e.g., NiCo), deposited by anelectrochemical plating process (e.g., electroplating). Similarly, theconductor layer 56 may also be deposited by an electrochemical platingprocess, such as electroplating.

A solder bump 60 is formed on the top surface 58 a of the barrier layer58. The solder bump 60 may be comprised of solder having a conventionallead-free (Pb-free) composition, which may include tin (Sn) as theprimary elemental component. In a representative embodiment, the solderbump 60 may be formed by electroplating using an appropriate platingsolution, anodes, and direct current. The barrier layers 54, 58,conductor layer 56, plug 41, adhesion layer 46, and adhesion layer 36provide a conductive path between the metal line 16 and the solder bump60. The barrier layer 58 may protect the material (e.g., Cu) of theunderlying plug 41 against consumption during reflow processes fromreactions with the solder bump 60.

With reference to FIG. 6 in which like reference numerals refer to likefeatures in FIG. 5 and at a subsequent fabrication stage, the platingmask 50 is stripped or otherwise removed from the top surface of theseed layer 48. For example, a stripping solution may be used if theplating mask 50 is comprised of a photoactive polymer resist, such asRISTON®. A solder bump connection 64 is defined by the structuresbetween the metal line 16 and the solder bump 60.

Field regions of the adhesion layer 46 and seed layer 48 are removedfrom the areas of the top surface 30 a of passivation layer 30 that arenot covered by the solder bump connection 64. Seed layer 38 is alsoremoved from within crackstop opening 30 by an etching process that isselective to the adhesion layer 36. The field regions of the adhesionlayer 36 may be removed using wet chemical etching processes with thealigned set of crackstop openings 28, 34 masked so that the adhesionlayer 36 is retained inside the crackstop openings 28, 34. During BEOLprocessing, the solder bump connection 64 is replicated across at leasta portion of the surface area of the wafer.

The solder bump 60 is reflowed and a flip-chip assembly process maythereafter be performed. The chip carrying the solder bump connection 64is inverted and aligned relative to a laminate substrate. The solderbumps, including solder bump 60, are bonded to the matching pads on thelaminate substrate using a reflow process. The temperature of the reflowprocess is dependent upon solder composition but is typically in a rangeof 200° C. to 300° C. Eventually, the solder bump 60 and solder bumpconnection 64 generate an electrical pathway for transferring datasignals to and from the chip to an external device, such as a computingsystem, or an electrical pathway for powering integrated circuits on thechip.

The method as described above is used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. Thechip may be integrated with other chips, discrete circuit elements,and/or other signal processing devices as part of either (a) anintermediate product, such as a motherboard, or (b) an end product. Theend product can be any product that includes integrated circuit chips,ranging from toys and other low-end applications to advanced computerproducts having a display, a keyboard or other input device, and acentral processor.

A feature may be “connected” or “coupled” to or with another element maybe directly connected or coupled to the other element or, instead, oneor more intervening elements may be present. A feature may be “directlyconnected” or “directly coupled” to another element if interveningelements are absent. A feature may be “indirectly connected” or“indirectly coupled” to another element if at least one interveningelement is present.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

What is claimed is:
 1. A solder bump connection comprising: apassivation layer; a via opening extending through the passivationlayer; and a plug in the via opening, wherein the plug is comprised of aconductor, the passivation layer includes a top surface that is coplanarwith the plug, and the top surface of the passivation layer is free ofsurface damage.
 2. The solder bump connection of claim 1 furthercomprising: a seed layer in the via opening, the seed layer comprised ofa material that promotes deposition of the conductor.
 3. The solder bumpconnection of claim 2 further comprising: a crackstop opening in thepassivation layer; and an adhesion layer disposed in the crackstopopening and disposed between the seed layer and the passivation layer inthe via opening, wherein the crackstop opening is free of the seedlayer.
 4. The solder bump connection of claim 1 further comprising: asolder bump; a dielectric layer; and a metal line in the dielectriclayer, wherein the solder bump is coupled with the metal line by theplug.